1. Field of the Invention
The present invention relates to a semiconductor substrate and a method of assembling semiconductor chips, and more particularly, to a method of assembling semiconductor chips including performing an electrical die sorting test on a semiconductor substrate having a plurality of semiconductor chips and physically separating the semiconductor chips.
2. Description of the Related Art
In general, a plurality of semiconductor chips is simultaneously manufactured in the form of a matrix on a semiconductor substrate, e.g., a silicon substrate. Each semiconductor chip divided by the matrix on a semiconductor substrate is called a die. After the operation to manufacture the semiconductor chips on the semiconductor substrate is completed, an electrical test for the respective semiconductor chips on the semiconductor substrate is performed, whereby defective semiconductor chips are detected.
The electrical test to detect defective dies is called an electrical die sorting (EDS) test. After the EDS test, an operation to assemble the semiconductor chips is performed.
Problems with the conventional EDS test and the assembly operation will be described referring to the accompanying drawings. Referring to FIG. 1, a semiconductor substrate 100 including semiconductor chips 10, 20, and 30 and others arranged in the form of a matrix is illustrated.
Some of the semiconductor chips 10, 20, and 30 formed on the semiconductor substrate 100 are excluded from the EDS test. For example, in FIG. 1, the semiconductor chips 20 and 30 inside an imaginary region 105 on the semiconductor substrate 100 are EDS test targets and the semiconductor chip 10 and other chips outside the imaginary region 105 are not EDS test targets. Since the semiconductor chips on the edge of the semiconductor substrate 100 are not perfectly patterned or correspond to a portion out of a process margin, they are considered to be defective from the beginning. The imaginary region 105 on the semiconductor substrate is not indicated in a real process.
Accordingly, when performing the EDS test or the assembly operation for the semiconductor substrate 100, the first semiconductor chip or die to be processed, for example the chip 20, is difficult to discriminate merely by its appearance. An alignment operation or other operations are performed using the first semiconductor chip or die 20 as a reference when the semiconductor substrate 100 is loaded on the EDS tester or an assembly device.
However, the first semiconductor chip needs an identification mark because there are many other semiconductor chips including the chips 10, 30 proximate to the first semiconductor chip 20. Referring to FIG. 2, a related art method for indicating the first semiconductor chip or die by using ink is illustrated. An ink mark is used mainly for indicating defective semiconductor chips after the EDS test rather than for indicating the first semiconductor chip. An ink mark 70 is positioned on a polyimide layer 60 that covers a passivation layer 55 on a silicon wafer 50. The thickness of the silicon wafer is about 674 μm, the polyimide layer is about 4 μm thick, and the ink is about 25 μm thick. An ink marking error occurs frequently because it is hard to distinguish the first semiconductor chip 20 in FIG. 1 from other semiconductor chips including the chips 10, 30 proximate to the first semiconductor chip 20.
Recently, products performing the assembly operation without the ink mark after the EDS test have been developed. In the case of a semiconductor substrate without an ink mark, the assembly operation is performed using the coordinate data of a semiconductor chip or die. Accordingly, the coordinates of the first semiconductor chip or die are especially important. Most products are processed without the ink mark due to reduction of the thickness of a back-lap and foundry businesses.
The indication of the first semiconductor chip or die on the substrate during the EDS test and the assembly operation becomes a very important issue. However, there have been frequent errors because the first die is not distinguishable from other dies in its appearance. In particular, there have been still frequent errors in pointing out the first die even though a limit sample is prepared and used as a guideline to accurately distinguish the first die.